In integrated circuit design, a commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
The metallization layers interconnecting individual devices typically comprise an inter-metal dielectric (IMD) layer in which interconnect structures, such as vias and conductive lines, are formed, through numerous and repetitive steps of deposition, patterning and etching of thin films on the surface of silicon wafers. While aluminum and aluminum alloys were most frequently used in the past for the metallization layers, the current trend is to use copper (Cu) for metallization layers because copper has better electrical characteristics than aluminum, such as decreased resistance, higher conductivity, and a higher melting point.
Nowadays, copper is commonly used in the damascene structures because of its low resistivity. Typically, copper is electro-plated into damascene openings. As is well known in the art, in order to plate copper, a seed layer is required to provide a low-resistance electrical path, and hence to enable uniform electro-plating over the wafer surface, so that copper ions in the plating solution can be deposited.
In most cases, prior art method for anisotropic trench etching and dual damascene formation has attempted to achieve substantially vertical sidewall profiles. After a copper seed layer is formed over sidewalls and a bottom of trench, a necking effect may occur due to the fact that on the sidewalls of trench, top portions of the seed layer are thicker than bottom portions, resulting in overhangs. Such overhang formations further constrict the opening dimension of the trench at the mouth portion thereof and consequently increases the likelihood of a “pinch-off” or “necking effect” and an attendant void formation. Inevitably, with the continual reductions in minimum feature sizes, the necking effect in a profile of seed layer will adversely affect the quality of the subsequently performed electro-plating.
Therefore, a novel mechanism to mitigate the aforementioned issues during a damascene operation has become an urgent need in fields pertinent to semiconductor manufacturing.